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FCCM
2009
IEEE

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

9 years 11 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-of-theart designs cannot support the current largest routing table (consisting of 257K prefixes in backbone routers). We propose a novel scalable high-throughput, low-power SRAMbased linear pipeline architecture for IP lookup. Using a single FPGA, the proposed architecture can support the current largest routing table, or even larger tables of up to 400K prefixes. Our architecture can also be easily partitioned, so as to use external SRAM to handle even larger
Hoang Le, Viktor K. Prasanna
Added 16 Aug 2010
Updated 16 Aug 2010
Type Conference
Year 2009
Where FCCM
Authors Hoang Le, Viktor K. Prasanna
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