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MJ
2006
145views more  MJ 2006»
13 years 6 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
DAC
2006
ACM
13 years 8 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
MSE
2002
IEEE
198views Hardware» more  MSE 2002»
13 years 11 months ago
BSS: A New Approach for Watermark Attack
Digital watermarking is the enabling technology to prove ownership on copyrighted material, detect originators of illegally made copies, monitor the usage of the copyrighted multi...
Jiang Du, Choong-Hoon Lee, Heung-Kyu Lee, Young-Ho...
DAC
2005
ACM
14 years 7 months ago
Minimising buffer requirements of synchronous dataflow graphs with model checking
Signal processing and multimedia applications are often implemented on resource constrained embedded systems. It is therefore important to find implementations that use as little ...
Marc Geilen, Twan Basten, Sander Stuijk
ICIP
2009
IEEE
14 years 7 months ago
Selective And Scalable Encryption Of Enhancement Layers For Dyadic Scalable H.264/avc By Scrambling Of Scan Patterns
This paper presents a new selective and scalable encryption (SSE) method for intra dyadic scalable coding framework based on wavelet/subband (DWTSB) for H.264/AVC. It has been ach...