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» Architectures and FPGA Implementations of the 64-Bit MISTY1 ...
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ISCAS
2008
IEEE
127views Hardware» more  ISCAS 2008»
13 years 11 months ago
Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection
— ICEBERG is a block cipher that has been recently proposed for security applications requiring efficient FPGA implementations. In this paper, we investigate a compact ASIC imple...
Huiju Cheng, Howard M. Heys
DAC
2001
ACM
14 years 5 months ago
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook K...
DAC
2005
ACM
14 years 5 months ago
High performance encryption cores for 3G networks
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
René Cumplido, Tomás Balderas-Contre...
CHES
2007
Springer
154views Cryptology» more  CHES 2007»
13 years 11 months ago
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert ...