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» Architectures for function evaluation on FPGAs
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ICES
2005
Springer
195views Hardware» more  ICES 2005»
13 years 11 months ago
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs
A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on t...
Jan Korenek, Lukás Sekanina
DAC
2002
ACM
14 years 6 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
IPPS
2002
IEEE
13 years 10 months ago
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs
This paper presents the implementation, on Virtex FPGAs, of a core generator for arbitrary numeric functions in fixed-point format. The cores use the state-of-theart multipartite...
Jérémie Detrey, Florent de Dinechin
FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
13 years 9 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan