76 search results - page 1 / 16 » Area Efficient Architectures for Information Integrity in Ca... |
ISCA
1999
IEEE
13 years 9 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
ANSS
2004
IEEE
13 years 8 months ago
2004
IEEE
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
ACSAC
2006
IEEE
13 years 8 months ago
2006
IEEE
Several secure computing hardware architectures using memory encryption and memory integrity checkers have been proposed during the past few years to provide applications with a t...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
FPGA
2000
ACM
13 years 8 months ago
2000
ACM
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...