22 search results - page 5 / 5 » Area Optimizations for Dual-Rail Circuits Using Relative-Tim... |
DAC
2010
ACM
13 years 9 months ago
2010
ACM
The emerging three-dimensional integrated circuit (3D IC) is beneficial for various applications from both area and performance perspectives. While the general trend in processor...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...