13 search results - page 2 / 3 » Area delay estimation for digital signal processor cores |
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
ICCD
2007
IEEE
14 years 2 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...