43 search results - page 3 / 9 » Area optimization of multi-cycle operators in high-level syn... |
DAC
1994
ACM
13 years 10 months ago
1994
ACM
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...
VLSI
2005
Springer
13 years 11 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
FCCM
2011
IEEE
12 years 9 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
FCCM
2002
IEEE
13 years 10 months ago
2002
IEEE
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
ISSS
1999
IEEE
13 years 10 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...