4 search results - page 1 / 1 » Area-Optimized Technology Mapping for Hybrid FPGAs |
FPL
2000
Springer
13 years 9 months ago
2000
Springer
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
FPGA
2006
ACM
13 years 9 months ago
2006
ACM
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...