15 search results - page 1 / 3 » Arithmetic Transformations to Maximise the Use of Compressor... |
DELTA
2004
IEEE
13 years 8 months ago
2004
IEEE
Complex arithmetic computations, especially if derived from bit-level software descriptions, can be very inefficient if implemented directly in hardware (e.g., by translation of t...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
CASES
2008
ACM
13 years 6 months ago
2008
ACM
The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device....
DCC
2004
IEEE
14 years 4 months ago
2004
IEEE
We report on a simple encoding format called wzip for decompressing block-sorting transforms, such as the Burrows-Wheeler Transform (BWT). Our compressor uses the simple notions o...