Sciweavers

34 search results - page 3 / 7
» Assertion-Based Design Exploration of DVS in Network Process...
Sort
View
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 4 days ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
IPPS
2008
IEEE
14 years 5 days ago
Modeling and analysis of power in multicore network processors
With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing signi...
S. Huang, Y. Luo, W. Feng
DAC
2009
ACM
14 years 6 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...
ICCAD
2000
IEEE
115views Hardware» more  ICCAD 2000»
13 years 10 months ago
Challenges and Opportunities in Broadband and Wireless Communication Designs
Communication designs form the fastest growing segment of the semiconductor market. Both network processors and wireless chipsets have been attracting a great deal of research att...
Jan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanf...
SAMOS
2005
Springer
13 years 11 months ago
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...