3 search results - page 1 / 1 » At-Speed Logic BIST for IP Cores |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...