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CODES
2003
IEEE
13 years 10 months ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
ICIP
2004
IEEE
14 years 6 months ago
Wyner-ziv video coding with hash-based motion compensation at the receiver
In current interframe video compression systems, the encoder performs predictive coding to exploit the similarities of successive frames. The Wyner-Ziv Theorem on source coding wi...
Anne Aaron, Shantanu Rane, Bernd Girod
ICIP
2007
IEEE
13 years 8 months ago
Motion-Based Side-Information Generation for a Scalable Wyner-Ziv Video Coder
A motion-based side-information generation scheme with semi super-resolution for a scalable Wyner-Ziv coder framework is introduced. It is known that the performance of any Wyner-...
Bruno Macchiavello, Ricardo L. de Queiroz, Debargh...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 8 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 6 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana