4 search results - page 1 / 1 » Automatic Design Validation Framework for HDL Descriptions v... |
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...