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ATS
2003
IEEE
98views Hardware» more  ATS 2003»
11 years 12 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an ef´Čücient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
FDL
2007
IEEE
12 years 28 days ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
12 years 3 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
12 years 20 days ago
Design with race-free hardware semantics
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
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