41 search results - page 1 / 9 » Automatic Generation of Synchronous Test Patterns for Asynch... |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exerc...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...
TCAD
2011
12 years 11 months ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...