9 search results - page 2 / 2 » Automatic Measurement of Instruction Cache Capacity |
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
ASPLOS
2009
ACM
14 years 5 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
CIKM
2006
Springer
13 years 9 months ago
2006
Springer
We propose to adapt the newly emerged cache-oblivious model to relational query processing. Our goal is to automatically achieve an overall performance comparable to that of fine-...
FPL
2005
Springer
13 years 10 months ago
2005
Springer
Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is requir...