Sciweavers

36 search results - page 3 / 8
» Automatic Verification of Pipelined Microprocessors
Sort
View
DATE
2010
IEEE
142views Hardware» more  DATE 2010»
13 years 7 months ago
Automatic microarchitectural pipelining
Abstract--This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct tra...
Marc Galceran Oms, Jordi Cortadella, Dmitry Bufist...
DAC
2007
ACM
14 years 6 months ago
Automatic Verification of External Interrupt Behaviors for Microprocessor Design
Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This pap...
Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang
IEEEPACT
2007
IEEE
13 years 11 months ago
Verification-Aware Microprocessor Design
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
Anita Lungu, Daniel J. Sorin
FAC
2000
124views more  FAC 2000»
13 years 5 months ago
Algebraic Models of Correctness for Microprocessors
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...
Anthony C. J. Fox, Neal A. Harman
TVLSI
2008
124views more  TVLSI 2008»
13 years 5 months ago
A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification
Abstract--We present a refinement-based compositional framework for showing that pipelined machines satisfy the same safety and liveness properties as their non-pipelined specifica...
Panagiotis Manolios, Sudarshan K. Srinivasan