89 search results - page 2 / 18 » Automatic and Efficient Evaluation of Memory Hierarchies for... |
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
HIPEAC
2010
Springer
13 years 3 months ago
2010
Springer
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
IEEEPACT
2008
IEEE
14 years 5 days ago
2008
IEEE
Achieving good performance on a modern machine with a multi-level memory hierarchy, and in particular on a machine with software-managed memories, requires precise tuning of progr...
ECRTS
2009
IEEE
13 years 3 months ago
2009
IEEE
Reader preference, writer preference, and task-fair readerwriter locks are shown to cause undue blocking in multiprocessor real-time systems. A new phase-fair reader-writer lock i...