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ICS
2009
Tsinghua U.
14 years 3 days ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron
ASPDAC
2006
ACM
124views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Functional modeling techniques for efficient SW code generation of video codec applications
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
CAISE
2004
Springer
13 years 10 months ago
Object-Process Methodology (OPM) vs. UML - a Code Generation Perspective
Modeling languages have been evolving at a high pace, encouraging the use of automatic code generators for transforming models to programs. Automatic code generators should enable ...
Iris Reinhartz-Berger, Dov Dori
DAGSTUHL
2007
13 years 6 months ago
Some Experiments on Tiling Loop Programs for Shared-Memory Multicore Architectures
The model-based transformation of loop programs is a way of detecting fine-grained parallelism in sequential programs. One of the challenges is to agglomerate the parallelism to a...
Armin Größlinger
SAMOS
2005
Springer
13 years 10 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...