96 search results - page 1 / 20 » Automatic generation of equivalent architecture model from f... |
DAC
2004
ACM
13 years 10 months ago
2004
ACM
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
TVLSI
2008
13 years 4 months ago
2008
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...