115 search results - page 3 / 23 » Automatic generation of transaction level models for rapid d... |
RSP
2003
IEEE
13 years 10 months ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
ESTIMEDIA
2007
Springer
13 years 11 months ago
2007
Springer
This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called ’event signatures’, op...
DATE
2009
IEEE
13 years 12 months ago
2009
IEEE
—The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space ...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....