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TECS
2008
122views more  TECS 2008»
13 years 6 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
14 years 26 days ago
UMTS MPSoC design evaluation using a system level design framework
Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design f...
Douglas Densmore, Alena Simalatsar, Abhijit Davare...
CODES
2006
IEEE
14 years 5 days ago
TLM/network design space exploration for networked embedded systems
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
Nicola Bombieri, Franco Fummi, Davide Quaglia
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 15 days ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
13 years 11 months ago
A New Performance Evaluation Approach for System Level Design Space Exploration
Application specific systems have potential for customization of design with a view to achieve a better costperformance-power trade-off. Such customization requires extensive de...
M. Balakrishnan, Anshul Kumar, C. P. Joshi