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» Automatic microarchitectural pipelining
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MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
13 years 11 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
FPGA
2006
ACM
178views FPGA» more  FPGA 2006»
13 years 9 months ago
Application-specific customization of soft processor microarchitecture
A key advantage of soft processors (processors built on an FPGA programmable fabric) over hard processors is that they can be customized to suit an application program's spec...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
MSCS
2008
86views more  MSCS 2008»
13 years 5 months ago
Maurer computers for pipelined instruction processing
We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing, using Maurer machines, basic thread algebra and program algebra. We sho...
Jan A. Bergstra, C. A. Middelburg