41 search results - page 1 / 9 » Automatic pipelining from transactional datapath specificati... |
DATE
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
DAC
2010
ACM
13 years 5 months ago
2010
ACM
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...