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MEMOCODE
2005
IEEE
13 years 11 months ago
Automatic synthesis of cache-coherence protocol processors using Bluespec
There are few published examples of the proof of correctness of a cache-coherence protocol expressed in an HDL. A designer generally shows the correctness of a protocol ny impleme...
Nirav Dave, Man Cheuk Ng, Arvind
MEMOCODE
2007
IEEE
13 years 11 months ago
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols
Orthogonal Frequency-Division Multiplexing (OFDM) has become the preferred modulation scheme for both broadband and high bitrate digital wireless protocols because of its spectral...
Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Da...
ISCA
1995
IEEE
147views Hardware» more  ISCA 1995»
13 years 8 months ago
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
Alvin R. Lebeck, David A. Wood
ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
13 years 12 months ago
SigRace: signature-based data race detection
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
Abdullah Muzahid, Darío Suárez Graci...
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 5 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...