86 search results - page 3 / 18 » Avoiding Shared Clocks in Networks of Timed Automata |
FORMATS
2008
Springer
13 years 7 months ago
2008
Springer
Time dependant models have been intensively studied for many reasons, among others because of their applications in software verification and due to the development of embedded pla...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
SLIP
2003
ACM
13 years 11 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
JSA
2008
13 years 5 months ago
2008
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
ICML
2010
IEEE
13 years 4 months ago
2010
IEEE
Classical dynamic Bayesian networks (DBNs) are based on the homogeneous Markov assumption and cannot deal with heterogeneity and non-stationarity in temporal processes. Various ap...