20 search results - page 4 / 4 » BIST Based Interconnect Fault Location for FPGAs |
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance....
ETS
2007
IEEE
13 years 11 months ago
2007
IEEE
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
DAC
2009
ACM
13 years 9 months ago
2009
ACM
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
14
Voted
GECCO
2008
Springer
13 years 5 months ago
2008
Springer
Scheduling collective communications (CC) in networks based on optimal graphs and digraphs has been done with the use of the evolutionary techniques. Inter-node communication patt...