31 search results - page 2 / 7 » Balanced Cache: Reducing Conflict Misses of Direct-Mapped Ca... |
EUROPAR
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Several schemes have been proposed that incorporate an auxiliary buffer to improve the performance of a given size cache. Victim caching, aims to reduce the impact of conflict mis...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
ICCD
2007
IEEE
13 years 9 months ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...