55 search results - page 2 / 11 » Balancing Logic Utilization and Area Efficiency in FPGAs |
FPL
2006
Springer
13 years 9 months ago
2006
Springer
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...