64 search results - page 3 / 13 » Bank-aware Dynamic Cache Partitioning for Multicore Architec... |
ICCS
2009
Springer
13 years 3 months ago
2009
Springer
Abstract. The efficient use of multicore architectures for sparse matrixvector multiplication (SpMV) is currently an open challenge. One algorithm which makes use of SpMV is the ma...
CF
2005
ACM
13 years 7 months ago
2005
ACM
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
HPCA
2007
IEEE
14 years 2 days ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
ISCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
IPPS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...