7 search results - page 1 / 2 » Bitwidth-aware scheduling and binding in high-level synthesi... |
DAC
1989
ACM
13 years 9 months ago
1989
ACM
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
TVLSI
2008
13 years 4 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...