29 search results - page 2 / 6 » Boolean Function Manipulation on a Parallel System Using BDD... |
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper describes an algorithm for the efficient solution of large systems of Boolean equations. The algorithm exploits the fact that, in some cases, the composition operation ...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
A special logic synthesis problem is considered for Boolean functions which have large don’t care sets and are irregular. Here, a function is considered as irregular if the inpu...
GLVLSI
1996
IEEE
13 years 9 months ago
1996
IEEE
Inthispaperweintroduceanondeterministiccounterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Reduced Ordered Binary Decision Diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions which are frequently used in VLSI Design Automation. ...