13 search results - page 2 / 3 » Boosting Beyond Static Scheduling in a Superscalar Processor |
EMSOFT
2008
Springer
13 years 7 months ago
2008
Springer
In this paper, we propose a generalized clustering approach for static data flow subgraphs mapped onto individual processors in Multi-Processor System on Chips (MPSoCs). The goal ...
ASPLOS
2012
ACM
12 years 1 months ago
2012
ACM
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to para...
APCSAC
2005
IEEE
13 years 11 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...