11 search results - page 2 / 3 » Bridge Fault simulation strategies for CMOS integrated Circu... |
MICRO
2006
IEEE
13 years 5 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...