69 search results - page 1 / 14 » Buffer insertion for clock delay and skew minimization |
ISPD
1999
ACM
13 years 9 months ago
1999
ACM
Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
ISLPED
2006
ACM
13 years 10 months ago
2006
ACM
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can ...