69 search results - page 13 / 14 » Buffer insertion for clock delay and skew minimization |
TVLSI
1998
13 years 5 months ago
1998
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
ISQED
2002
IEEE
13 years 10 months ago
2002
IEEE
All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the ...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations pr...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
VLSID
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...