69 search results - page 2 / 14 » Buffer insertion for clock delay and skew minimization |
ICCAD
2010
IEEE
13 years 3 months ago
2010
IEEE
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock sk...
ISQED
2010
IEEE
14 years 8 days ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
GLVLSI
2009
IEEE
14 years 4 days ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
DAC
2010
ACM
13 years 3 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
INTEGRATION
2008
13 years 5 months ago
2008
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...