13 search results - page 1 / 3 » Buffered Steiner tree construction with wire sizing for inte... |
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
ASPDAC
1998
ACM
13 years 9 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
ISVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...