4 search results - page 1 / 1 » Buffered clock tree synthesis for 3D ICs under thermal varia... |
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
ASPDAC
2012
ACM
12 years 16 days ago
2012
ACM
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
TCAD
2010
12 years 11 months ago
2010
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...