56 search results - page 2 / 12 » Buffering global interconnects in structured ASIC design |
TCAD
2010
12 years 12 months ago
2010
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and b...