5 search results - page 1 / 1 » Built in Defect Prognosis for Embedded Memories |
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
MTDT
2000
IEEE
13 years 9 months ago
2000
IEEE
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...