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» Built-in test generation for synchronous sequential circuits
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VTS
1999
IEEE
114views Hardware» more  VTS 1999»
13 years 9 months ago
Partial Scan Using Multi-Hop State Reachability Analysis
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting propagating these target faults. Add...
Sameer Sharma, Michael S. Hsiao
DAC
2000
ACM
14 years 6 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy
MEMOCODE
2007
IEEE
13 years 11 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
EUROMICRO
2000
IEEE
13 years 9 months ago
Concurrent Control Systems: From Grafcet to VHDL
The Automated Production Systems (APS) are composed of concurrent interacting entities. Then any model should exhibit parallel and sequential behaviours. The Grafcet is now well e...
Frédéric Mallet, Daniel Gaffé...