18 search results - page 1 / 4 » Bus-aware microarchitectural floorplanning |
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Abstract-- In this paper we present the first bus-aware microarchitectural floorplanning. Our goal is to study the impact of bus routability on other important floorplanning object...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
— In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design ...