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» CAD Directions for High Performance Asynchronous Circuits
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DAC
1994
ACM
13 years 8 months ago
A Modular Partitioning Approach for Asynchronous Circuit Synthesis
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
Ruchir Puri, Jun Gu
VLSID
2005
IEEE
87views VLSI» more  VLSID 2005»
14 years 5 months ago
Synthesis of Asynchronous Circuits Using Early Data Validity
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Nitin Gupta, Doug A. Edwards
ICCAD
2002
IEEE
163views Hardware» more  ICCAD 2002»
14 years 1 months ago
Sub-90nm technologies: challenges and opportunities for CAD
Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practi...
Tanay Karnik, Shekhar Borkar, Vivek De
ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
13 years 10 months ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
VLSI
2005
Springer
13 years 10 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...