5 search results - page 1 / 1 » CELLERITY: A Fully Automatic Layout Synthesis System for Sta... |
DAC
1997
ACM
13 years 8 months ago
1997
ACM
This paper describes a fully automatic standard-cell layout synthesis system, CELLERITY. The system is flexible in supporting a wide variety of process technologies and a range of...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
In order to efficiently design complex microelectromechanical systems (MEMS) having large numbers of multi-domain components, a hierarchically structured design approach that is ...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...