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» CHIPS: Custom Hardware Instruction Processor Synthesis
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ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
13 years 6 months ago
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
Siew Kei Lam, Thambipillai Srikanthan
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
13 years 8 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
13 years 11 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
SASP
2008
IEEE
77views Hardware» more  SASP 2008»
13 years 11 months ago
Resource Sharing in Custom Instruction Set Extensions
Abstract—Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must ta...
Marcela Zuluaga, Nigel P. Topham
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
13 years 10 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...