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» CMOS gate modeling based on equivalent inverter
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ICCAD
1994
IEEE
121views Hardware» more  ICCAD 1994»
13 years 9 months ago
A cell-based power estimation in CMOS combinational circuits
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
13 years 11 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
DELTA
2010
IEEE
13 years 10 months ago
A More Precise Model of Noise Based PCMOS Errors
—In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy ...
Arun Bhanu, Mark S. K. Lau, Keck Voon Ling, Vincen...
SBCCI
2004
ACM
100views VLSI» more  SBCCI 2004»
13 years 10 months ago
Design of RF CMOS low noise amplifiers using a current based MOSFET model
This paper presents a design methodology for RF CMOS Low Noise Amplifiers (LNA). This methodology uses a current–based MOSFET model, which allows a detailed analysis of an LNA f...
Virgínia Helena Varotto Baroncini, Oscar da...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 5 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy