Sciweavers

869 search results - page 3 / 174
» Cache Architectures for Reconfigurable Hardware
Sort
View
FCCM
2002
IEEE
321views VLSI» more  FCCM 2002»
13 years 10 months ago
Queue Machines: Hardware Compilation in Hardware
Abstract - In this paper, we hypothesize that reconfigurable computing is not more widely used because of the logistical difficulties caused by the close coupling of applications a...
Herman Schmit, Benjamin A. Levine, Benjamin Ylvisa...
IPPS
2006
IEEE
13 years 11 months ago
A stochastic multi-objective algorithm for the design of high performance reconfigurable architectures
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
Wing On Fung, Tughrul Arslan
FPL
2007
Springer
78views Hardware» more  FPL 2007»
13 years 11 months ago
Dynamic Cache Switching in Reconfigurable Embedded Systems
The idea of changing cache attributes to suit an application has been explored for single programs. As the popularity of reconfigurable softcore systems grows and these systems in...
John Shield, Peter Sutton, Philip Machanick
FPL
2009
Springer
145views Hardware» more  FPL 2009»
13 years 10 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
13 years 10 months ago
Parallel Processing Architectures for Reconfigurable Systems
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
Kees A. Vissers