27 search results - page 1 / 6 » Cache Array Architecture Optimization at Deep Submicron Tech... |
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
HPCA
2002
IEEE
14 years 4 months ago
2002
IEEE
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
DAC
1999
ACM
13 years 8 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...