27 search results - page 3 / 6 » Cache Array Architecture Optimization at Deep Submicron Tech... |
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
ICCD
2002
IEEE
14 years 2 months ago
2002
IEEE
With technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large onchip array structures such as caches and branch predictors. Recent...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...